In a 3D chip stack there might be thousands of interconnections communicating vertically between chips in the stack. It is important that the chips in the stack are tested before integration. If they are not tested, the yield of the assembled chip stack could be overly degraded. In many circumstances probe testing of the I/O might not be practical, for a variety of reasons. For example, the probe pitch is likely to be very fine, making the probe card expensive. The microbumps could be damaged by the probe tips. The large number of I/Os being tested could also result in an expensive probe card. In addition, more high speed test channels might be required in the tester equipment, increasing its cost. Nevertheless, it remains important to speed-test the I/Os to ensure desired performance.
In the figures, like reference numerals refer to the same figure elements.